Adders are known in the art and are generally used to add a particular number of bits of equal significance, with the sum value (in the form of a sum bit) and a particular number of requisite carry bits being output. By way of example, “three-to-two bit full adders” are known, said adders having three inputs for receiving three bits of equal significance w and two outputs for outputting a sum bit of significance w and a carry bit of significance 2w. In this case, the sum bit of significance w indicates the parity of the sum of the three input bits of significance w, and the carry bit indicates the carry of significance 2w. Further carry outputs are required if more than three bits of equal significance are to be added. In order to make the most efficient use possible of the representational space for the carry bits, it is appropriate to output a sum bit and two carry bits of significance 2w and 4w when adding seven bits of equal significance.
EP 0514061 describes a “seven-to-three bit adder”. In this case, the input bits of equal significance that are to be added are routed to the outputs through six logic gate stages.
The present invention is now based on the object of providing a simple multibit adder. In particular, the adder is to require little implementation complexity and is to have particularly short signal propagation times and a low power consumption.